1. Field of the Invention
The present invention relates generally to methods for forming trench fill layers within trenches within substrates employed in integrated circuit fabrication. More particularly, the present invention relates to methods for forming gap filling ozone assisted chemical vapor deposited (CVD) silicon oxide trench fill layers within trenches within substrates employed in integrated circuit fabrication.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
As integrated circuit technology has advanced and integrated circuit device dimensions have decreased, it has become increasingly common within advanced integrated circuits to employ trench isolation methods such as shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods to form trench isolation regions nominally co-planar with adjoining active semiconductor regions of semiconductor substrates. Such trench isolation methods typically employ a chemical mechanical polish (CMP) planarizing method to provide a nominally planarized surface to a trench isolation region formed from a trench fill dielectric layer formed within the trench. Trench isolation regions nominally co-planar with active semiconductor regions within semiconductor substrates are desirable since they optimize, when subsequently forming patterned layers upon those nominally co-planar trench isolation regions and active semiconductor regions, the limited depth of focus typically achievable with advanced photoexposure tooling.
When forming within advanced integrated circuits trench isolation regions within isolation trenches, it has become common to employ as trench fill dielectric layers gap filling silicon oxide layers formed through ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) methods and ozone assisted atmospheric pressure chemical vapor deposition (APCVD) methods. Silicon oxide layers formed through such methods are desirable since such silicon oxide layers possess inherently superior gap filling characteristics desirable for trenches of limited dimensions typically encountered in advanced integrated circuit fabrication.
While gap filling silicon oxide layers formed through ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) methods and ozone assisted atmospheric pressure chemical vapor deposition (APCVD) methods are thus desirable as trench fill layers within trenches within advanced integrated circuit fabrication, methods through which are formed such gap filling silicon oxide layers are not entirely without problems. In particular, it is known in the art that gap filling silicon oxide layers formed through ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) methods exhibit a surface sensitivity dependent upon the substrate layers upon which are formed those gap filling silicon oxide layers. In particular, when employing as substrate layers thermally grown silicon oxide layers which are typically employed as isolation trench liner layers within isolation trenches formed within semiconductor substrates, gap filling silicon oxide layers formed through ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) methods exhibit inhibited formation rates. Inhibited formation rates within isolation trenches within semiconductor substrates of gap filling silicon oxide trench fill layers formed through ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) methods are undesirable since there is then formed within those isolation trenches gap filling silicon oxide trench fill layers which are particularly susceptible to dishing when subsequently planarized through chemical mechanical polish (CMP) planarizing methods.
It is thus towards the goal of forming within advanced integrated circuits gap filling silicon oxide trench fill layers formed through ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) methods, while avoiding a surface sensitivity, that the present invention is generally directed.
Methods and materials through which isolation regions may be formed within isolation trenches for use within integrated circuits are known in the art of integrated circuit fabrication. For example, Nasr et al., in U.S. Pat. No. 5,346,584 disclose a planarization method employing an oxidized patterned polysilicon filler layer as a trench fill layer when forming an isolation region within an isolation trench within a semiconductor substrate. The oxidized patterned polysilicon filler layer provides a relatively planar semiconductor substrate surface which is readily planarized through a chemical mechanical polish (CMP) planarizing method. In addition, Figura et al., in U.S. Pat. No. 5,472,904 disclose a method for simultaneously forming a narrow trench isolation region and a recessed oxide isolation (ROI) region within a semiconductor substrate. The method employs an oxidation barrier formed within a narrow trench within which is formed the narrow trench isolation region, but not within a wide trench within which is formed the recessed oxide isolation region. Finally, Bose et al., in U.S. Pat. No. 5,492,858 disclose a method for forming a planarized trench fill dielectric layer within an isolation trench within an integrated circuit. The method employs within the isolation trench a barrier layer which allows for densifying, through steam annealing, a conformal silicon oxide trench fill dielectric layer which may then subsequently be planarized, while avoiding dishing, through a chemical mechanical polish (CMP) planarizing method.
Desirable in the art are additional methods through which trenches within substrates employed within integrated circuit fabrication may be filled with gap filling silicon oxide trench fill layers formed through ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) methods, while avoiding a surface sensitivity. Particularly desirable are additional methods through which isolation trenches within semiconductor substrates employed within integrated circuit fabrication may be filled with gap filling silicon oxide trench fill dielectric layers formed through ozone assisted sub-atmospheric chemical vapor deposition (SACVD) methods, while avoiding a surface sensitivity. It is towards these goals that the present invention is more specifically directed.